As digital logic devices become smaller they become more sensitive to the effects of electronic noise, such as electronic thermionic noise. The extremely high clock frequency of these devices, together with the high speeds of conventional microprocessors, create a system environment that is increasingly noisy. Thus, data in these high speed systems becomes more vulnerable to errors caused by transient electrical and electromagnetic phenomena.
In digital logic circuits, the effects of electronic noise are often manifested as random single errors. To detect these random errors, a checking circuit is required. One approach is to duplicate the hardware and compare the two results, which, of course, is expensive in duplicated circuitry and space on the integrated circuit.
Another approach is to use error detection and error correction techniques. Parity checking is a commonly-used technique for error detection where a parity bit, or check bit, is added to a group of data bits. The check bit may be asserted depending on the number of asserted data bits within the group of data bits. If even parity is used, the parity bit will make the total number of asserted bits, including the data bits and the check bit, equal to an even number. If odd parity if used, the parity bit will make the total number of asserted bits, including the data bits and the check bit, an odd number. As shown in FIG. 1, parity checking in this case is accomplished by generating 130 a parity bit, i.e., adding the number of data bits having a value of “1” in the data 125 calculated and then adding the parity bit or bits required to get the desired odd or even total for the transmitted data unit. The checking device 150 receives the data 145 and calculates the parity bit or bits required to give the desired odd or even total for the received data unit. If the parity bit or bits calculated 155 by the checking device 150 matches the parity bit or bits of the data 145, then the data is good. If the calculated parity bit or bits 155 does not match the parity bit or bits of the data, then there is a parity error in the received data. From the above it should be understood that parity checking is only effective for detecting an odd number of errors. If an even number of errors occurs, however, parity checking will not detect the error.
Another method of parity checking uses odd or even parity as well. In parity prediction, as shown in FIG. 2, the parity bit is predicted 230 at the same time that the data is calculated 220. A special parity prediction circuit 230 is used. The calculated data 245 is then checked 250 for a correct parity bit. As in FIG. 1, if the calculated parity 255 matches the parity of the data 245, then the calculated data is good. If the calculated parity bit 255 does not match the parity bit of the data 245, then the calculated data 245 has at least one error. As in FIG. 1, it should be understood that, due to the nature of its error checking process, simple parity error checking has a 50% probability of detecting data errors.
It is readily known that a single parity bit in conjunction with a multiple bit data word is useful for detecting an odd number of bit errors within the data word. Therefore, there is a need for a fast parity generating circuit that can be implemented cheaply on a digital logic circuit.